Volatile storage elements such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access memory), and nonvolatile memory such as FLASH are used in a variety of fields.
However, memory which has the high speed, low voltage properties of DRAM and the nonvolatile properties of FLASH memory, such as FeRAM (Ferro-electric Random Access Memory), MRAM (Magnetoresisitive Random Access Memory) and PRAM (Phase change Random Access Memory), is currently being researched. Some of these memories are also in mass production.
FeRAM elements include ferroelectric capacitors constructed by sandwiching a ferroelectric layer between upper and lower electrodes on a substrate. FeRAM makes use of a hysteresis property in a relationship between a polarization charge and voltage in ferroelectric materials.
Ferroelectric capacitors may be classified into planar types and stack types according to a connection structure of the lower electrode and the transistor connection. In the planar type, wiring connected to an upper surface of the lower electrode electrically connects to either the source or drain of a transistor. In the stack type, a conductive plug connected to a lower surface of the lower electrode connects to either the source or drain of the transistor.
The stack-type ferroelectric capacitor is formed using a process shown in FIGS. 1A-1D. An example of such a process is disclosed in Japanese Patent Application Laid-Open No. HEI10-12832.
In FIG. 1A, a transistor tr used to form FeRAM is formed on a silicon substrate (silicon wafer) 101. The transistor tr includes a gate electrode 103 formed on the silicon substrate 101 with a gate insulating film 102 there between, source/drain impurity-diffused regions 104a and 104b formed in the silicon substrate 101 on both sides of the gate electrode 103, and an interlayer insulating film 105 formed on the gate electrode 103 and the source/drain impurity diffused regions 104a and 104b. Contact holes 106 are formed in the interlayer insulating film 105 on the source/drain impurity diffused regions 104a and 104b, and conductive plugs 107a and 107b composed of polysilicon are formed in the contact holes 106.
After forming a barrier metal layer 108, an Ir lower electrode layer 109, a TiOx seeding layer 110a, and a non-crystalline PZT layer 110b, a PZT crystalline layer 110 is formed by annealing the TiOx seeding layer 110a and the non-crystalline PZT layer 110b in an oxygen atmosphere, as shown in FIG. 1B.
Next, after forming an Ir upper electrode layer 111 on the PZT crystalline layer 110 as shown in FIG. 1C, a mask (not shown in the drawings) is formed on the Ir upper electrode layer 111 and etching is performed from the upper electrode layer 111 to the barrier metal layer 108. The arrangement remaining under the mask, composed of layers from the Ir upper electrode layer 111 to the barrier metal layer 108, forms a capacitor 112.
The barrier metal layer 108 formed under the Ir lower electrode layer 109 is formed to prevent the conductive plugs 107a and 107b from reacting with the Ir lower electrode layer 108, and is composed of a material such as TiN, RuO2, TiAlN. TiAlN has excellent oxygen resistance and functions as a thin film oxygen barrier layer.
After forming a multitude of FeRAMs on a substantially circular silicon wafer, the silicon wafer is divided to form chips.
The lower electrode layer 109 in the FeRAM is prevented from forming on a peripheral edge part of the silicon wafer 101 by using a shadow ring (not shown in the drawings), as shown in FIG. 2A. Moreover, the Ir lower electrode layer 109 is formed more thinly on the peripheral edge part of the silicon wafer 101, and in some cases, is removed by etching to prevent film peeling at the peripheral edge part.
As a result, the Ir lower electrode layer 109 is absent from the peripheral edge part of the silicon wafer 101, and, when a TiAlN layer is formed as the barrier metal, the PZT crystalline layer 110 contacts the barrier metal layer 108 at the peripheral edge part of the silicon wafer 101, as shown in FIG. 2B.
However, adhesion of the PZT crystalline layer 110 to the TiAlN barrier metal layer 108 is poor, and portions of the PZT crystalline layer 110 tend to lift or peel. This is considered to be a result of expansion caused by a reaction between the TiAlN barrier metal layer 108 and Pb in the PZT crystalline layer 110 which occurs at a crystallization temperature of the PZT crystalline layer 110.
The PZT crystalline layer 110 peeling from the peripheral edge part of the silicon wafer 101 in this way may cause contamination in subsequent processes, resulting in deterioration in semiconductor element yield rate.